This invention relates in general to word line drivers and, more particularly, to a BICMOS memory word line driver.
Memory circuits are typically arranged in a row/column alignment where the memory cells are divided into logical blocks, say sixty-four bits wide and eighty bits deep. The memory circuit overall may contain many memory blocks. Each memory cell (one bit) is addressable by the combination of a word line and a column line which selects the x-coordinate and y-coordinate of a single memory cell. There are sixty-four word line drivers for the 64.times.80 bit memory block, one for each row of eighty memory cells.
A conventional word line driver comprises p-channel and n-channel MOS transistors arranged as an inverter with common gates. A BLOCKcontrol signal activates sixty-four word line drivers associated with a particular memory block. Thus, the BLOCKcontrol signal is continuously loaded by the gate capacitance of sixty-four inverting transistor pairs. A plurality of MAXI control signals enable respective word line drivers across all memory blocks. For example, one MAXI control signal may enable the first word line driver in every memory block. The combination of the BLOCKcontrol signal and one MAXI control signal selects one word line driver and, correspondingly, a group of eighty memory cells. BIT and BITdata signals then write to and read from the desired memory cell.
A principal problem with the prior art word line drivers is the unbalanced loading between the BLOCKcontrol signals and the MAXI control signals. The BLOCKcontrol signal drives sixty-four word line drivers (gate capacitance of at least 128 transistors), while each MAXI control signal may drive only four memory blocks (gate capacitance of eight transistors). The propagation delay for the BLOCKcontrol signal is much longer than the propagation delay of the MAXI control signals. The operating speed of the memory circuit is thus limited by the slower propagation rate of the BLOCKcontrol signal.
Another drawback with prior art word line drivers is the strict MOS transistor implementation. The output drive capacity of MOS transistors is much less than other technologies such as bipolar, given similar geometries.
Hence, what is needed is an improved word line driver having reduced propagation delay for the BLOCKcontrol signal while providing higher output drive to enable the memory cells.